PCIe Gen5 to Gen6: What Changes in Your Component BOM
Published: June 13, 2026 | Category: AI & Data Center
Moving from PCIe Gen5 to PCIe Gen6 is not a routine speed upgrade. PCIe 5.0 operates at 32 GT/s per lane using NRZ signaling, while PCIe 6.0 reaches 64 GT/s per lane using PAM4. PCI-SIG also introduced FLIT mode and low-latency forward error correction to support the higher raw error rate associated with PAM4. For AI servers, accelerator platforms, storage systems, switches, NICs, and other high-performance data-center hardware, these changes affect far more than the processor or connector choice.
At the procurement level, Gen6 changes the signal-chain BOM. Retimers become more important, clocking requirements tighten, PCB laminate and connector quality matter more, passive-component selection must be reviewed carefully, and validation equipment becomes part of the project cost. The challenge for purchasing teams is that many of these parts are specialized, qualification-intensive, and difficult to substitute once the layout is frozen.
This guide explains what changes in a PCIe Gen6 BOM, which components deserve early sourcing attention, and how procurement teams can reduce redesign and shortage risk before a Gen6 platform reaches mass production.
PCIe Gen6 Changes More Than the Data Rate
The headline specification is straightforward: Gen5 operates at 32 GT/s per lane, while Gen6 doubles that to 64 GT/s. The important architectural change is PAM4. Instead of using two voltage levels as NRZ does, PAM4 uses four levels and carries two bits per symbol. That allows PCIe 6.0 to double the transfer rate without simply doubling the symbol rate.
This matters because PAM4 has smaller eye openings and less voltage margin than NRZ. The channel therefore becomes more sensitive to insertion loss, reflections, crosstalk, connector discontinuities, package effects, and clock quality. PCIe 6.0 also uses FLIT-based operation and FEC to achieve reliable links at the higher raw bit-error environment.
For procurement, the practical lesson is simple: components that were treated as secondary BOM items in a Gen4 or Gen5 design may become critical-path items in Gen6.
Retimers Move to the Center of the BOM
At lower PCIe generations and over shorter channels, designers may be able to close the link budget using careful routing, connectors, and sometimes redrivers. Gen6 platforms often need a more capable signal-conditioning strategy, particularly across complex server topologies, risers, backplanes, cables, accelerator trays, or multi-connector paths.
A retimer is fundamentally different from a redriver. A redriver provides analog signal conditioning, while a retimer recovers the clock and data and retransmits a new signal. That makes retimers better suited to recovering heavily degraded high-speed links.
For PCIe 6.x, suppliers such as Astera Labs offer DSP-based retimers designed for 64 GT/s PAM4 links. Astera's Aries 6 family, for example, is positioned for PCIe 6.x and CXL 3.x connectivity in AI and cloud infrastructure.
Procurement Risk: Retimers Are Not Commodity Parts
Retimers should be treated as strategic components. Important differences include lane count, host and endpoint topology, package, power, management interface, firmware, telemetry, interoperability behavior, and software support. A part from another vendor is rarely a drop-in substitute.
Before design freeze, procurement should ask engineering:
Is a retimer required on every Gen6 path or only selected channels?
How many lanes must each device support?
Is the board layout tied to one supplier footprint?
Does the design depend on vendor-specific firmware or management software?
Has a second retimer vendor been electrically and mechanically evaluated?
What validation is required after a retimer substitution?
The earlier these questions are answered, the easier it is to avoid a single-source bottleneck during AI-server ramp.
Do Not Assume a Fixed Lead Time for PCIe Gen6 Retimers
High-speed connectivity devices can experience strong demand during data-center deployment cycles, but published lead times change rapidly. Procurement teams should avoid building their sourcing plan around a fixed assumption such as “20–30 weeks” unless it has been confirmed for the exact manufacturer part number and production window.
A better approach is to obtain current factory or authorized-channel lead-time information, track allocation status, and maintain forecast visibility with the supplier. If a retimer is both single-sourced and layout-critical, purchasing may also consider approved safety stock or scheduled orders aligned with the platform ramp.
PCB Material Becomes a System-Level Sourcing Decision
PCIe Gen6 increases the importance of board dielectric loss, copper roughness, stack-up consistency, via design, connector transitions, and route length. Standard high-loss PCB constructions that worked comfortably at slower generations may not provide enough margin for a long or complex Gen6 path.
However, it is too simplistic to say that “FR-4 is impossible” for every Gen6 design. FR-4 is a broad material category, and actual channel performance depends on route length, stack-up, connector count, loss budget, equalization, and whether retimers are used. Short channels can have very different requirements from large server backplanes or accelerator baseboards.
In practice, many high-performance Gen6 platforms evaluate low-loss laminates such as Panasonic Megtron-class materials, Isola Tachyon-class materials, or comparable high-speed PCB systems. The correct laminate should be selected from a validated channel model rather than from a generic material rule.
Procurement Questions for PCB Material
Which exact laminate family and resin system are approved?
Is an equivalent material from a second PCB supplier qualified?
What dielectric constant and dissipation-factor ranges are assumed in simulation?
What copper-foil roughness is allowed?
How tightly must finished impedance be controlled?
Are back-drilling or advanced via structures required?
Can every intended PCB factory hold the specified stack-up tolerances?
For procurement managers, the risk is not only laminate availability. A board house may offer a nominally similar material but have different process capability, glass weave, copper treatment, or thickness tolerances that shift signal-integrity performance.
Connectors, Cables, and Riser Cards Need Gen6 Qualification
At Gen6, every interconnect discontinuity consumes channel margin. Connectors that were acceptable at Gen5 should not automatically be assumed to pass Gen6. The same applies to riser cards, board-to-board connectors, cable assemblies, MCIO-type interconnects, and other high-speed links used in AI servers.
Purchasing should avoid substituting connectors based only on pin count and mechanical similarity. High-speed validation can depend on insertion loss, return loss, crosstalk, contact geometry, plating, connector footprint, and PCB launch design.
For cable-based architectures, active solutions may also appear in the BOM. Retimer-based active electrical cable architectures can extend reach, but they add power, firmware, thermal, and supplier dependencies that must be managed like other active components.
Clocking: Tight Jitter Requirements Change the Supplier List
Reference-clock quality is another area where Gen6 platforms require more careful engineering. High-performance server designs may use dedicated clock generators, jitter cleaners, buffers, and timing devices rather than simple low-cost oscillators.
Devices such as TI's LMK04832 demonstrate the class of ultra-low-noise clocking components used in demanding high-speed systems, with specified RMS jitter in the tens-of-femtoseconds range under defined integration bandwidths. The exact clock solution for PCIe Gen6 must still be selected against the PCIe clock architecture, jitter budget, output format, spread-spectrum requirements, and platform topology.
For procurement, the important point is that clock parts are no longer interchangeable simply because they produce the same nominal frequency.
Clocking BOM Checks
Reference-clock architecture
Output count
Output signaling standard
Phase-noise and integrated-jitter requirements
Spread-spectrum support
Power-supply noise sensitivity
Package and thermal requirements
Clock-buffer second-source strategy
If a design uses a specialized jitter cleaner or clock generator, procurement should flag it as a high-risk line item early in NPI.
AC-Coupling Capacitors: Follow the Specification and the Channel Model
PCIe differential links use AC coupling, but component selection should follow the PCIe specification, platform reference design, and signal-integrity simulation rather than a blanket rule such as “always use 220 nF C0G.” Capacitance value, package size, placement, parasitics, and routing geometry all affect the channel.
At very high data rates, the package and mounting structure of the capacitor can matter as much as the nominal capacitance. Small packages can reduce parasitic inductance, but manufacturability, availability, voltage rating, and land pattern must also be considered.
Procurement teams should preserve the engineering-approved dielectric, package, tolerance, and manufacturer list. A generic same-capacitance replacement should not be released without electrical review if the capacitor sits directly in a Gen6 high-speed lane.
Power Delivery Also Expands
Retimers, switches, clock devices, and other Gen6 infrastructure add power rails and thermal load. This can increase demand for point-of-load converters, multiphase controllers, power stages, inductors, low-ESR capacitors, and monitoring devices.
AI platforms already place heavy stress on power architecture. A connectivity upgrade can therefore create secondary BOM changes that are easy to miss when teams focus only on the PCIe signal path.
Procurement should request a delta BOM between the Gen5 and Gen6 versions of the platform. This makes it easier to identify newly introduced power components before those devices become sourcing bottlenecks.
PCIe Gen5 vs Gen6: Procurement-Level BOM Comparison
| BOM Area | PCIe Gen5 | PCIe Gen6 | Procurement Impact |
|---|---|---|---|
| Signaling | 32 GT/s NRZ | 64 GT/s PAM4 | Higher SI sensitivity |
| Retimers | Topology dependent | More important on demanding channels | Potential single-source risk |
| PCB material | Low-loss material often used on long paths | Tighter loss-margin requirements | More laminate and fab qualification |
| Connectors/cables | Gen5-qualified parts | Gen6 validation required | Fewer acceptable substitutions |
| Clocking | High-quality reference clock | Tighter system jitter budget | Specialized timing components |
| Passives | Controlled high-speed BOM | More sensitive to parasitics and placement | AVL discipline becomes more important |
| Validation | NRZ channel validation | PAM4, FLIT/FEC-aware platform validation | Longer qualification cycle |
Validation Equipment Becomes Part of the Project Budget
A Gen6 design may require more advanced channel simulation, compliance testing, high-bandwidth oscilloscopes, fixtures, analyzers, and interoperability validation. Even if the OEM outsources some testing, procurement should understand that these costs and schedules are part of the component-selection decision.
An alternate connector or retimer that appears cheaper may become more expensive if it requires a new validation cycle. For this reason, total cost of change is a more useful metric than unit price alone.
How to Source PCIe Gen6 Components Without Creating a Future Line Stop
The highest-risk Gen6 components should be identified during NPI. A useful sourcing classification is based on three factors: supplier concentration, redesign difficulty, and lead-time volatility.
Components that score high on all three dimensions deserve early action. Typical candidates include retimers, PCIe/CXL switches, specialized clocking devices, high-speed connectors, low-loss PCB materials, and certain power devices.
Procurement can then apply the appropriate strategy:
Confirm the exact MPN and revision. High-speed parts often have meaningful suffix, firmware, or stepping differences.
Check authorized supply first. Obtain current factory lead times and allocation status.
Lock the AVL before mass production. Avoid casual substitutions of signal-path components.
Qualify second sources where practical. This may mean a second vendor rather than a pin-compatible device.
Use scheduled orders for long-lead components. Align supply with server-platform ramp forecasts.
Maintain traceability. High-value retimers and clock components should have clear sourcing documentation.
Require engineering approval for brokered alternates. Similar specifications do not guarantee interoperability.
Do Not Buy Gen6 Parts from the Base Part Number Alone
For advanced data-center components, the full ordering code matters. Lane count, package, temperature grade, firmware, speed grade, security features, and hardware revision can change within one product family.
A purchasing RFQ should include:
Full manufacturer part number
Required revision or stepping
Firmware requirement where applicable
Quantity and forecast
Target delivery schedule
Approved date-code range
Packaging requirement
Whether alternates may be proposed
Required traceability
For a Gen6 server or accelerator project, submitting the complete high-speed BOM can be more effective than requesting one retimer. The same platform may contain multiple constrained clock, connector, PMIC, switch, memory, and passive components.
Where Procurement Teams Commonly Make Mistakes
Mistake 1: Treating Gen6 as a faster Gen5 BOM. The signaling architecture changes enough that several previously flexible components become tightly controlled.
Mistake 2: Assuming every channel requires the same solution. A short on-board path may have a very different BOM from a cable, riser, backplane, or multi-connector path.
Mistake 3: Locking one retimer vendor without a lifecycle plan. If the footprint, firmware, and management architecture are vendor-specific, switching later can require significant redesign.
Mistake 4: Buying “equivalent” connectors or passives without SI review. At Gen6 speeds, mechanical equivalence does not guarantee electrical equivalence.
Mistake 5: Ignoring PCB-fabricator capability. The laminate alone does not guarantee performance. Process control, copper roughness, drilling, back-drilling, stack-up, and impedance control all matter.
How Aurora Components Supports PCIe Gen6 and AI Data-Center BOM Sourcing
Aurora Components Co., Limited supports OEMs, EMS providers, engineering teams, and procurement departments sourcing electronic components for AI servers, data-center platforms, telecom equipment, storage systems, networking hardware, and high-speed computing applications.
PCIe Gen6 projects can involve retimers, switches, clock generators, jitter cleaners, power-management ICs, connectors, memory, capacitors, inductors, and other specialized components from multiple manufacturers. If one critical component becomes constrained, the entire platform schedule can be affected.
Aurora Components can assist with BOM sourcing, hard-to-find electronic components, shortage requirements, obsolete and EOL parts, alternative sourcing, and multi-manufacturer procurement. For high-value connectivity components sourced outside authorized channels, buyers should define traceability, packaging, inspection, date-code, and revision requirements before purchase.
If your PCIe Gen6, CXL, AI accelerator, storage, or server platform is entering NPI or mass production, send the exact part numbers or complete BOM for sourcing review.
Designing PCIe Gen6 hardware? Submit your BOM / RFQ to Aurora Components.
Website: www.auroraic.com
Email: info@auroraic.com
